This invention relates to a display technique for a display, and in particular relates to a technique for displaying an image by illuminating pixels of a display unit.
An example of such display is a plasma display which is of interest because it can easily be adapted to large panels.
In this plasma display, the sub field method is generally used wherein intermediate gradations between light-emitting and non-light emitting are displayed. In this method, one field period is formed from plural periods to which unique light-emitting weightings are assigned, and brightness gradation is represented by controlling the illumination and non-illumination of pixels (cells) in each sub field. In a plasma display wherein an address operation which specifies pixels to be illuminated and a sustain operation, wherein the specified pixels are illuminated (made to emit light), are performed at different times, i.e., the so-called address/sustain separation method, one sub field period comprises a reset period which initializes the state of the cells (pixels), an address period which controls the illumination/non-illumination of the cells (pixels), and a sustain period which determines the light amount emitted by each cell when it is illuminated. These periods are respectively controlled by control pulses having a predetermined time width.
In the address period, address processing is performed corresponding to lines based on data which controls the illumination/non illumination of the pixels, so with high-resolution panels which have a large number of lines, the address period requires a considerable time. If it is attempted to deal with this problem by shortening the sustain period, sufficient brightness cannot be obtained due to the reduction of pixel light-emitting time, and if it is attempted to deal with a problem by reducing the number of sub fields in one field period, a sufficient gradation cannot be obtained. For example, it is attempted to construct a high resolution panel having a vertical resolution of 1000 lines where the address processing time is 2 xcexcs per line, an address period of 2 ms (=2 xcexcsxc3x971000 lines) per sub field is required. In general, it is said that a gradation of about 256 (8 bits) is required to display an image without deterioration of the image signal. If eight sub fields are formed in one field period (approx. 16.6 ms) using this 2 ms address period per sub field, the total address period in one field is 16 ms (=2 msxc3x978), so nearly all of one field period is taken up by the address period. As a result, there is practically no time left to allot to the sustain period in one field period, so not enough time is available for panel illumination and the brightness of the image decreases. Also, if the number of sub fields is decreased from, for example, 8 to 6, and the number of gradations is decreased from 256 to 64, a sufficient number of gradations cannot be displayed and the image quality deteriorates.
Another problem inherent in the sub field method is that of false contour which causes the quality of moving images to degenerate. To reduce false contour, the distribution and center of light emission in one field is usually controlled. If the number of gradations that can be displayed is fixed, the number of light-emitting patterns that can be controlled may be increased by increasing the number of sub fields and there is then a large false contour reduction, but if a sufficient number of sub fields cannot be obtained, it is difficult to reduce false contours.
In the prior art display apparatus, the aim was to faithfully display the input signal, and techniques were used to improve image quality taking account of human visual characteristics, such as dither or error scatter processing to partially compensate for insufficient number of gradations, or control of average brightness, but all these techniques only controlled signal amplitude.
An example of the related art is that of Japanese Unexamined Patent Publication No. Hei 11-24628. In this publication, a technique is disclosed for shortening the address period by interlace scanning in sub fields corresponding to lower bits, and also a method for performing a write-in operation by selecting two scanning electrodes simultaneously instead of interlace scanning, but the specific signal-generating technique used is not disclosed.
Each line of the image signal is data sampled in the vertical direction of one screen, and in order to interpolate the sampling data by interlace scanning, the vertical resolution must first largely be reduced to, for example, one half so as to reduce clinch disturbance. In other words, in the prior art interpolation of sampling data, the resolution of the display panel could not be maintained and a high-quality display could not be obtained.
If sampling data was interpolated without largely reducing the vertical resolution to about half beforehand, high frequency signal components were converted to low-frequency signal components due to clinch disturbance and image quality deteriorated.
If the lower bits of adjacent upper and lower data are unconditionally made the same, the display data may largely vary and image quality may considerably deteriorate. For this reason, some kind of processing is necessary. For example, with upper and lower adjacent pixel data , when the upper pixel data is level 16 and the lower pixel data is level 15, in a sub field representation with a light-emission weighting having a power of 2, level 16 is represented by [1,0,0,0] (1 is a light-emitting sub field and 0 is a light extinction sub field starting from the upper sub field), and level 15 is [0,1,1,1,]. Here, assuming the same data by interpolating the sub fields corresponding to the lower three bits at a rate of one line in two according to interlace criteria, the lower three sub fields [1,1,1] of level 15 [0,1,1,1] of the lower pixel are replaced by the lower three sub fields [0,0,0] of level 16 [1,0,0,0,] of the upper pixel. As a result, the level which is displayed is [0,0,0,0], and a pixel at level 15 becomes a pixel at level 0. Conversely, if the lower three sub fields [1,0,0,] of level 16 of the upper pixel are replaced using the lower three sub fields [1,1,1] of level 15 of the lower pixel, the upper pixel at level 16 becomes level 31 [1,1,1,1]. This extreme level fluctuation is responsible for flicker.
This invention aims to suppress this type of level fluctuation and decrease of resolution by, for example, performing processing so that data in predetermined sub fields becomes the same, and for example processing lower sub fields by referring to signals for common, plural lines.
It is therefore an object of this invention to solve the above problems inherent in the prior art, and to provide a display technique which can produce a high resolution, finely graded image.
To achieve the above object, in this invention, the necessary number of sub fields and display period length are achieved by making full use of human visual characteristics and the statistical characteristics of the image signal, and limiting the amount of resolution information in the display image to shorten the address period.
This invention therefore provides the following:
1) A display apparatus which displays an image by illuminating pixels of a display unit, the apparatus comprising an input signal processing circuit which processes an input image signal, a control circuit which controls display resolution information relating to an image displayed on the display unit, and a drive circuit which drives the display unit based on the outputs of the input signal processing circuit and control circuit, wherein an image corresponding to the input image signal is displayed by driving the display unit with the drive circuit when the display resolution information is limited by the control circuit, and the illuminated pixel selection time of the display unit is shortened.
2) A display apparatus using a sub field which illuminates addressed pixels of a display unit to display an image, comprising an image signal processing circuit which performs sub field conversion processing on an input image signal, a control circuit which controls display resolution information of an image displayed on the display unit and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the input signal processing circuit and control circuit, wherein an image corresponding to the input image signal is displayed by driving the display unit with the drive circuit when the display resolution information is limited by the control circuit, and the address period which selects the illuminated pixels of the display unit is shortened.
3) A display apparatus using a sub field which illuminates addressed pixels of a display unit to display an image, comprising a display unit on which the pixels are arranged in plural lines,an image signal processing circuit which converts an input image signal into sub field data showing illumination or extinction of each sub field, a smoothing circuit which performs control so that bit data of the sub field data are arranged in the plural lines of the display unit, a control circuit which controls the address periods of the sub fields so as to arrange the bit data, and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the image signal processing circuit, smoothing circuit and control circuit, wherein the image is displayed by driving the plural lines of the display unit while performing control to shorten address periods in predetermined sub fields, and arranging the bit data.
4) A display apparatus using a sub field which illuminates addressed pixels of a display unit to display an image, comprising a display unit on which pixels are formed in intersecting parts where first line electrodes and second line electrodes are arranged to intersect, a conversion circuit which converts an input image signal to sub field data, a smoothing circuit which performs control so that bit data of the sub field data are arranged in plural lines of second line electrodes of the display unit, a control circuit which controls the address periods of the sub fields in which the bit data are arranged, and a drive circuit which forms a drive signal that drives the display unit based on the output of the control circuit, addresses pixels by driving at least the first line electrodes and illuminates the addressed pixels by driving the second line electrodes, wherein the image is displayed by driving the plural lines of second line electrodes of the display unit while controlling address periods in predetermined sub fields, and arranging the bit data.
5) A display method for displaying an image by illuminating pixels of a display unit, comprising an input signal processing step for processing an input image signal, a control step for controlling display resolution information of an image displayed on the display unit and a drive step for driving the display unit based on the outputs formed by the input signal processing step and control step, wherein an image corresponding to the input image signal is displayed by driving the display unit when the display resolution information is limited and the illuminated pixel selection time of the display unit is shortened.
6) A display method using a sub field for illuminating addressed pixels of a display unit to display an image, comprising an image signal processing step for performing sub field conversion processing on an input image signal, a control step which controls display resolution information of an image displayed on the display unit, and a drive step which addresses and illuminates pixels of the display unit based on the outputs of the input signal processing step and control step, wherein an image corresponding to the input image signal is displayed by driving the display unit when the display resolution information is limited by the control circuit, and the address periods are shortened.
7) A display method using a sub field for addressing and illuminating pixels of a display unit on which the pixels are arranged in plural lines so as to display an image, comprising an image signal processing step for converting an input image signal into sub field data showing illumination or extinction of each sub field, a smoothing step for performing control so that bit data of the sub field data are arranged in the plural lines, a control step for controlling address periods of the sub fields in which the bit data are arranged, and a drive step for addressing and illuminating pixels of the display unit based on the outputs of the image signal processing step, smoothing step and control step, wherein the image is displayed by driving the plural lines of the display unit while controlling address periods in predetermined sub fields, and arranging the bit data.
8) A control-drive circuit for driving a display apparatus which displays an image by illuminating pixels of a display unit, comprising an input signal processing circuit which processes an input image signal, a control circuit which controls display resolution information of an image displayed on the display unit, and a drive circuit which drives the display unit based on the outputs of the input signal processing circuit and control circuit, wherein an image corresponding to the input image signal is displayed by driving the display unit with the drive circuit when the display resolution information is limited by the control circuit, and the illuminated pixel selection time of the display unit is shortened.
9) A control-drive circuit for driving a display apparatus using a sub field which illuminates addressed pixels of a display unit to display an image, comprising an image signal processing circuit which performs sub field conversion processing on an input image signal, a control circuit which controls display resolution information of an image displayed on the display unit, and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the input signal processing circuit and control circuit, wherein the display resolution information in predetermined sub fields is limited by the control circuit, and the address periods of the display unit are shortened by the drive circuit.
10) A control-drive circuit for a display apparatus using a sub field which illuminates addressed pixels of a display unit to display an image, comprising an image signal processing circuit which converts an input image signal into sub field data showing illumination or extinction of each sub field, a smoothing circuit which performs control so that bit data of the sub field data are arranged in plural lines of the display unit, a control circuit which controls address periods of the sub fields to arrange the bit data, and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the image signal processing circuit, smoothing circuit and control circuit, wherein a drive output which controls address periods in predetermined sub fields and arranges the bit data is obtained as an output for driving the plural lines of the display unit.